- Experienced Physical Design engineers to oversee the P&R process of core IPs and complex subsystems.
- Engineer will be responsible for owning tapeouts of Blocks/Chips and integrates implementation environment components utilizing advanced flows and latest P&R tools.
- Implementing complex IP/ASIC.
- Responsible for Netlist to GDS physical design implementation of complex chips/blocks.
- Responsible of signoff tasks, including power integrity, signal integrity, RC correlation and layout signoff flow in physical design team.
Technical hands-on capability and strong related P&R experience. Preferably Synopsys flows/tools He/She should have experience in complete block level implementation (2M plus) and top level integration experience or MACRO implementation experience.
Implemented large blocks with more than 30% area with memories. Good at design closure (congestion, timing and physical verification) Block/Chip PD, exposure to multi-million gate design (>2million instances with 100+ memories) in recent technologies (32nm,28nm,20nm…). Desired experience using Synopsys ICC with good TCL scripting skills. Desired experience using Synopsys PT Integration/Physical Verification: desired chip finish experience using Mentor Caliber for DRC/LVS, handling multi-million hier designs, along with good understanding of the sign-off checks, EM/IR, XTalk, DFM.
Three Plus year of experience required.
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